The present invention relates to a thin film transistor (TFT) and in particular, to a thin film transistor having a vertical channel in which the satisfactory channel length in less area can be obtained and the leakage current can be reduced when it is in OFF state.
A conventional TFT presently used in semiconductor devices such as a static random access memory (SRAM), liquid crystal display (LCD), etc. has a planar channel generally. In general, such TFT is fabricated by a conventional method including steps of forming a gate electrode on the insulation layer, forming a gate insulation film on the gate electrode, forming a silicon layer on the gate insulation film, and forming channel, source and drain areas by ion implantation processes respectively. However, it is difficult to apply such conventional method in manufacturing SRAM because of increasing the unit cell area. In manufacturing LCD requiring high resolution, increase in unit cell area is caused to deteriorate the resolution. Also, in the case of minimizing the channel length to reduce the unit cell area, it is a problem that the leakage current increases when such fabricated TFT is in OFF state.